Samsung Electronics has given its 8-inch foundry customers a hard date: every line that still makes chips on 200-millimetre wafers will be shut down by the end of 2030. The deadline was reported on November 2 by Korean semiconductor outlet The Elec, citing industry sources, and it is the first time Samsung has put a year on a wind-down it had previously described only as “gradual.” The word 파운드리 (foundry) climbed into Korea’s Google search trends the next day, and Korean fabless chip designers started doing arithmetic.
What is actually closing
A foundry makes chips to other companies’ designs. Samsung’s foundry division is best known for its race with TSMC at the bleeding edge, but it also runs three older 8-inch fabs in Giheung, south of Seoul, named S6, S7 and S8. These lines use mature process nodes from 65 to 180 nanometres, technology Samsung first put into mass production between 2000 and 2011, and they produce display driver ICs, power management chips, microcontrollers and image sensors.
According to The Elec, Samsung decided early in 2026 to close S7 by the end of this year while keeping S6 and S8 running, and it stopped taking orders for new 8-inch products the same year. On its first-quarter earnings call in April, foundry vice president Kang Seok-chae said the 8-inch lines for power semiconductors, driver ICs and image sensors would be shut down in sequence. The 2030 notice simply tells customers when “in sequence” ends. Staff and capital spending are to be redirected to advanced 12-inch production.
Why Korean chip designers are nervous
The customers named in the report are Korean fabless firms: LX Semicon, Silicon Mitus, ABOV Semiconductor, Dongwoon Anatech and Imagis. They chose 90 to 180 nanometre nodes because those are the cheapest way to make analog and power chips, and shrinking an analog design onto a 12-inch advanced line is not a matter of pressing “export.” It typically means a redesign, higher costs and a fresh round of qualification with every end customer.
The obvious fallback, moving the orders down the road, is not easy either. Korea’s two specialist 8-inch foundries, DB HiTek and SK Keyfoundry, have most of their capacity committed to existing clients. The Asia Business Daily reported in January that DB HiTek’s utilisation had risen into the mid-to-high 90 percent range, up from about 70 percent at the end of 2024, and that its new Sangwoo expansion of 35,000 wafers a month is not expected to reach full production until late 2027 at the earliest. Taiwanese fabs have little spare room, and Chinese foundries are off-limits for some end customers that restrict Chinese-made components. The Elec quotes one industry official summarising the bind: “domestic capacity is full, China is not an option.”
This is a global squeeze, not just a Korean one. TSMC is reportedly moving roughly 80 percent of its annual 8-inch output, about five million wafers, to affiliate Vanguard International Semiconductor in phases. Research firm TrendForce expects average 8-inch utilisation at the world’s top ten foundries to approach 90 percent in 2026, from around 80 percent in 2025, and to stay above 80 percent through the first half of 2027. Bargaining power on mature-node wafers, in other words, has quietly shifted from buyers to the dwindling number of sellers. Some fabless firms have responded the old-fashioned way, by stockpiling chips, which solves the supply problem by creating a cash and warehouse problem.
What happens next
Four years is a long notice period by industry standards, and one official quoted by The Elec conceded it was hard to call the decision unilateral. Still, Korean fabless companies are lobbying for a delay and floating the idea of government involvement, on the grounds that individual designers have little leverage over Samsung. Watch for three things: whether Samsung softens the 2030 date for specific product lines, whether DB HiTek’s Sangwoo capacity arrives on schedule, and whether Seoul’s industry ministry treats mature-node supply as a strategic issue rather than a commercial one. For a country whose chip strategy is usually discussed in terms of two-nanometre bragging rights, the near-term problem turns out to be 180-nanometre plumbing.